1. Field of the Invention
The present invention relates to a flash memory, a memory control circuit, a microcomputer and a memory control method, and particularly, to a flash memory, a memory control circuit, a microcomputer and a memory control method, in which a writing operation and a reading operation of data is carried out by using an additional bit.
2. Description of the Related Art
In recent years, a semiconductor device having nonvolatile memories of a flash memory and an EEPROM (Electrically Erasable Programmable only Memory) has been used. Although being the nonvolatile memories, the flash memory and the EEPROM are different from each other in characteristics such as a data erasure unit, a number of times of rewrite times and circuit area.
To write data in the flash memory or the EEPROM, new data cannot be written unless data stored in a memory cell in the flash memory or the EEPROM is first erased. The flash memory and the EEPROM are different in an erasure unit. In the flash memory, data stored therein is erased in units of blocks, while in the EEPROM the data stored therein is erased in units of memory cells which can be selected by a word line and a bit line (hereinafter, the unit is referred to as a minimum write unit). For this reason, the flash memory which can erase data therein only in units of blocks has a limited usage in comparison with the EEPROM.
The flash memory and the EEPROM also have different number of times of the rewrite or erasure. For example, in case of a microcomputer, the flash memory guarantees the number of times of rewrite of about 100 to 1000, while the EEPROM guarantees the number of times of rewrite of about 10,000 to 100,000. In terms of the erasure unit and the number of times of rewrite or erasure, it is considered that the EEPROM is technically superior to the flash memory. However, to guarantee a circuit configuration for enabling erasure in the minimum write unit and the number of times of rewrite of 10 to 1,000 times as many as that of the flash memory, the EEPROM requires a device configuration capable of resisting influence of high electric field applied at the time of erasure, resulting in increases in size of the circuit. Since the increase in size of the circuit leads to increase in manufacturing cost, it is deemed that the flash memory is superior to the EEPROM from this point of view.
Therefore, the nonvolatile memories of the flash memory and the EEPROM are provided in the semiconductor device. While, a large amount of data with low frequency of rewrite is stored in the flash memory, a small amount of data with high frequency of rewrite is stored in the EEPROM. By using the flash memory and the EEPROM for different purposes in this manner, advantages of both of the flash memory and the EEPROM are effectively utilized.
However, a manufacturing process of the semiconductor device in which the multiple types of memories having different structures are mounted is complicated. In comparison with a manufacturing process of the semiconductor device in which only the one of the memories is mounted, the former manufacturing process requires addition of a lot of steps, thereby increasing the manufacturing cost. Therefore, a method has been devised of avoiding the complicated process while using only the flash memory as the nonvolatile memory and handling a part of the flash memory as the EEPROM. The method of using the flash memory like the EEPROM is generally called as an EEPROM emulation.
According to the EEPROM emulation, by utilizing an unused area of a storage area in the flash memory, that is, a free (blank) area where no data is written to a maximum extent and erasing data in units of blocks after use of all areas, the number of times of erasure accompanying data update is reduced, thereby increasing the virtual number of times of rewrite as in the EEPROM.
FIG. 1A shows a case where data A stored in the EEPROM is rewritten (updated) to data A′ and FIG. 1B shows a case where the data A stored in the flash memory is rewritten (updated) to data A′. When the data A is rewritten to the data A′, the data A′ should be generally overwritten over the data A. However, since a writing operation cannot be performed without erasing data in the flash memory and the EEPROM, specifically, electric charges are removed (erased) from floating gates of all memory cell which exist in units of blocks or the minimum write unit. Then, an electric charge is injected (written) to the floating gate of an arbitrary memory cell based on data to be written to carry out rewrite. Since the erasure unit of the EEPROM is the minimum write unit, as shown in FIG. 1A, by erasing the data A to be rewritten and writing the data A′ at the same location, rewrite of the data A into the data A′ in the EEPROM is completed.
On the other hand, when the data A, B and C have been written in one block as shown in FIG. 1B the data B and C are erased at the same time if the whole block is erased to overwrite the data A since the rewrite unit of the flash memory is the block unit. Thus, by temporarily saving the data B and C in another area and writing the data A′, B and C after erasure in the block, the rewrite of the data A to the data A′ in the flash memory is completed.
However, in the EEPROM emulation, when a free (blank) area in which the data A′ can be written exists as shown in FIG. 1B), the data A′ is written into the blank area. Since the data A and A′ coexists, the data A is invalidated as an invalid data according to a predetermined method. In use of the EEPROM emulation, erasure in units of blocks becomes unnecessary as long as a blank area for writing new data. Furthermore, temporary saving and rewriting of the other data (corresponding to data B and C in FIG. 2) which accompanies the block erasure can be avoided. That is, the number of times of rewrite or erasure can be reduced, and the virtual number of times of rewrite can be increased as in the EEPROM. Moreover, data can be rewritten without considering protection of the other data as in the EEPROM.
Next, referring to FIGS. 2 to 7, the EEPROM emulation will be described in detail. FIG. 2 shows a data write unit in the conventional EEPROM emulation (hereinafter referred to as emulation write unit). Data contained in the emulation write unit is composed of n+1 data of DATA_0 to DATA_n and a data number (ID) as a name of a group of n+1 DATA (that is, the ID is data associated with a plurality of data). A value of the ID must be a value other than a value in the erased state, that is, a value read from the free area. The number of data (n) in each data group must be common for each ID and must not have different values. For example, when the number of data contained in a data group O to which the identification number ID=0 is assigned is 5, the number of data contained in a data group 1 to which the identification number ID=1 must be 5. A plurality of data forming the emulation write unit are collectively referred to as a data group.
FIG. 3 is a flow chart showing a writing process in the conventional EEPROM emulation. FIGS. 4, 5 and 6 each show a flash memory that stores the data group 0 to the data group 2 therein. The flash memory in FIGS. 4, 5 and 6 is formed of one block (that is, the erasure unit is a whole flash memory) and has minimum write unit areas (addresses) of 0000H address to FFFFH address. The size of the data that can be stored in each address is 8 bits (00H to FFH). The data groups 0 to 2 are written in addresses 0000H to address 00011H. The data group 0 to the data group 2 are each formed of the DATA_0 to DATA_4 and the ID (ID=0 to 2). If the erased state of the flash memory is represented as FFH, as described above, since the ID must be a value other than the value read out from the data area in the erased state, the possible values of the ID are 00H to FEH. As shown in FIG. 2, an area where the DATA and ID are stored is defined as a data area.
Referring to FIGS. 3, 4, 5 and 6, a writing process in the EEPROM emulation and an example of a process of writing the data group 1 will be described. As shown in FIG. 3, the writing process is carried out in two stages of a blank search for identifying an area where new data is written (S13-1 to S13-4) and of sequentially writing DATA_0 to ID in the identified blank area (S13-1 to S13-6).
At a step S13-1, starting from an address FFFFH as a last address in the flash memory, data is read in the search direction of the address FFFFH→address FFFEH→address FFFDH→ . . . →address 0001H→address 0000H. That is, the data is read out from the side of the blank area in the flash memory in FIG. 2.
At a step S13-2, it is determined whether or not the read value is a value other than FFH (FFH is a value representing the erased state (unused free state)). When the value other than FFH is read, the process proceeds to a step S13-4. On the other hand, when FFH is read, the process proceeds to the step S13-3.
At the step S13-3, the read address is decremented by +1 (since the search direction is from the last address toward a start address, the read address is incremented by −1). The same shall apply hereinafter, and the reading operation is performed again. In FIG. 4, since the area of the address FFFFH to an address 0012H is an unused (blank) area, the process at the steps S13-2 and S13-3 is repeated up to the address 0012H.
At a step S13-4, when a value other than FFH is read at step S13-2, an address read immediately before the address at which the value other than FFH is read is identified as a head address of the blank area (write start address) when data other than FFH is read, a boundary between the used area and the unused (blank) area can be identified. Thus, the address where FFH is finally read can be determined as the head address of the blank area.
In FIG. 4, since the ID=2 (value other than FFH) is read at an address 00011H, the address 00011H is determined as the last address (boundary address) between the used area, and the address 0012H is determined as the address read immediately before the last address is determined as the head address of the blank area. As described above, the possible values of the ID are 00H to FEH. If the value of the ID is FFH, it cannot be distinguished from the blank area. Thus, FFH must not be used as the value of the ID.
At a step S13-5, the data (DATA_0 to DATA_n) are written. The writing operation is performed in the order of DATA_0→DATA_1→ . . . →DATA_n. In FIG. 5, The DATA_0 to DATA_4 in the data group 0 are written.
At a step S13-6, the ID is written. The ID is written at the end of an emulation write unit. Thus, when the ID is written, a series of writing processes of the data groups having a plurality of data is completed.
In FIG. 6, the writing process of the ID=1 in the data group 0 is completed and the writing process of the data group 1 composed of the DATA_0 to DATA_4 and the ID=1 is completed. The writing process in the conventional EEPROM emulation is performed in this way. Then, when new data group is written, an additional writing process is performed by using the same steps. In FIG. 6, the new data group is written at an address 0018H. Also, in FIG. 4, although the written data groups 0 to 2 exist, the writing operation is performed from an address 0000H when no data group has been written. Furthermore, when blank searching reveals that the blank area is lack for writing all data contained in the data group, an erasing operation becomes necessary, and the erasing operation needs to be performed while protecting necessary data, as described above.
Next, a reading operation in the conventional EEPROM emulation will be described. FIG. 7 is a flow chart showing a conventional reading process. As shown in FIG. 7, the reading process is performed in two stages of an ID search process (steps S17-1 to S17-6) for identifying the data group to be read by searching the ID associated with a plurality of data contained in the data group, and a read process (S17-7) of the identified data group from the flash memory. As a specific example, the reading process of the data groups 0 and 1 from the flash memory shown in FIG. 6 will be described. However, since the second writing process of the data group 1 (data update) is performed in the flash memory shown in FIG. 6, the data group 1 (address 0012H to address 0017H) written last time is a valid data group and the data group 1 (address 0006H to address 0008H) written previously is dealt as an invalid data group.
At a step S17-1, starting from an address FFFFH as a last address in the flash memory, data is read in the search direction of the address FFFFH→address FFFEH→address FFFDH→ . . . →address 0001H→address 0000H. That is, the data is read out from the side of the blank area in the flash memory in FIG. 6. This process is the same as the step S13-1 in the above-described writing process.
At a step S17-2, it is determined whether or not the read value is a value other than FFH (FFH is a value representing the erased state). When the value other than FFH is read, the process proceeds to a step S17-4. On the other hand, when FFH is read, the process proceeds to a step S17-3.
At a step S17-3, the read address is decremented by 1 and the reading operation is performed again. In FIG. 6, since the area of the address FFFFH to the address 0018H is an unused (blank) area, the process at the steps S17-2 and S17-3 is repeated up to the address 0018H.
At a step S17-4, when a value other than FFH is read, it is determined whether or not the read value is the ID associated with the DATA in the data group to be read (target ID). In FIG. 6, if the data group to be read is the data group 0, the ID can be determined as the target ID when the read value is the ID=0. At the step S17-2, a value other than FFH is detected at an address 0017H and the value stored at the address 0017H is the ID=1. Thus, since the data group to be read is the data group 0, determination is made that the read value is not the target ID. On the other hand, if the data group to be read is the data group 1, the read value can be determined as the target ID since the data stored at the address 0017H is the ID=1.
At a step S17-5, when the read value is not the target ID, a reading process is performed at the address decremented from the read address by +6 again. Then, it is determined whether or not the read value is the target ID at the step S17-4. In FIG. 6, when the data group to be read is the data group 0, the address decremented from the address 0017H by +6 is an address 00011H. Since the value read at the address 00011H is the ID=2, the read value is not the target ID (ID=0). Accordingly, the read address is decremented by +6 again.
At a step S17-6, when the read value is the target ID at the step S17-4, the address decremented from the address where the target ID is read by +5 is identified as the head address of the data group to be read. In FIG. 6, when the data group 0 is read, an address 0000H decremented from the address 0005H by +5 is identified as the head address of the data group to be read since determination is made that the target ID is stored at an address 0005H at S17-4. When the data group 1 is read, an address 0012H decremented from the address 0017H by +5 is identified as the head address of the data group to be read since determination is made that the target ID is stored at the address 0017H at S17-4.
At a step S17-7, the DATA_0 is read from the head address of the data group that is identified at the step S17-6 and the DATA_1 to DATA_n are read sequentially while incrementing the address by +1. In FIG. 6, by reading the DATA_0 to DATA_4 from the address 0000H to address 0004H, the reading process of the data group 0 is completed. By further reading the DATA_0 to DATA_4 from the address 0012H to address 0016H, the reading process of the data group 1 is completed.
The data group 1 is updated in the flash memory shown in FIG. 6. Data of the data group 1 are stored at two locations and the valid data group is the data group written at later time, that is, closer to the blank area side. According to the method described at the steps S17-1 to S17-6, the ID is searched from the blank area side, and when the read value becomes equal to the target ID, search of the data group to be read is finished. Thus, even when a plurality of data groups having the same ID are stored in the flash memory, the newest data group, that is, the valid data group can be read.
Also, in an example of a reading process by using the data group 1 as the data group to be read in FIG. 6, the valid data group 1 (the address 0012H to address 0017H) is selected without selecting the invalid data group 1 (the address 0006H to address 0008H).
In the writing process flow in FIG. 3 and the reading process flow in FIG. 7, the blank search and the ID search are performed from the address FFFFH (last address). On the contrary, the search may be performed from the address 0000H (start address). However, in this case, in the writing process flow, the address obtained by incrementing the address where the value other than FFH is finally read by +1 is defined as the head address of the unused (blank) area. In the reading process, only ID is read by incrementing the read address by +6, and it is determined whether or not the read value is the target ID in the reverse direction from the ID read immediately before at the time when the read value is FFH. In this manner, the target ID can be identified.
A technique concerning such EEPROM emulation is disclosed in “Application Note U17057JJ3VOAN00” (the third edition, NEC Electronics Corporation, November, 2004, pp. 25-27). In this application note, the emulation write unit is formed of a data number, a data 1, a delimiter, and a data 2, and FFH (erased state) must not be used as the data number. The data number is stored in the flash memory every four bytes. By reading the data number while incrementing from the head of a block for every four bytes, the newest data is searched. When a plurality of data numbers having the same number are found, data closest to an end of data is dealt as a newest data.
As described above, in the reading process of the data group written by using the EEPROM emulation, the data number (ID) associated with each emulation write unit (the data group) is searched, and it is determined whether or not the searched ID is the ID of data to be read. At this time, when the storage location of the ID in the data written in the flash memory cannot be found, the ID cannot be searched. For this reason, conventionally, by making the number of data contained in the emulation write unit (the data group) same, the ID is regularly stored at each address in the flash memory, thereby allowing ID search. In FIG. 5, in the data group 0 to the data group 2, the emulation write unit (the data group) is composed of 6 data of the ID and the DATA_0 to DATA_4, and the ID is regularly arranged and written in the flash memory every six addresses.
However, it is a limit in product design in the viewpoint from a user and is a substantial disadvantage that the number of data of the emulation write unit must be common (a fixed value) in all emulation write units (the data groups). If the value used as the ID is prohibited from being used as values of the DATA_0 to DATA_n, the ID can be searched even when the number of data in the emulation write unit (the data group) is not common (a fixed value) in all emulation write units (the data groups). However, this limits the values of the DATA_0 to DATA_n used by the user, which is unpractical.